This invention relates to arithmetic units for use in digital computers and digital data processors for adding and subtracting binary coded decimal numbers.
The present invention is concerned with the processing of numerical data represented by sequences of binary digits or bits. In the described embodiment, the data bits in these binary bit sequences are grouped into 8 bit groups and each such 8 bit group is called a "byte." For purposes of detecting the occurrence of erroneous data, a parity check bit is associated with each 8 bit data byte during various portions of the journey of the data bytes through the data processing machine. Where odd parity checking is used, the value of the parity check bit is assigned so as to give the overall 9 bit combination formed by the 8 data bits and the one parity check bit and odd number of binary 1 level bits. If, on the other hand, even parity checking is used, the parity check bit is set so as to cause the overall 9 bit combination to have an even number of binary 1 level bits. A parity check is performed at various places in the data processor by detecting the number of 1 level bits in each 9 bit combination. If odd parity is being used and an even number of 1 bits are detected, then that piece of data is known to contain an error and the appropriate error-handling routine can be called into play. The same considerations apply where even parity is being used and an odd number of 1 bits is detected.
At certain points in a data processor, the data bits must be separated from the check bits and processed by themselves. An example of this occurs in the case of a binary adder in an arithmetic unit. In such case, only the data bits for the two numbers to be added are supplied to the adder and new parity check bits must be generated for the resultant data bits appearing at the output of the adder. This can and has been done for arithmetic units which handle purely binary data by locating the appropriate parity check bit generating circuitry at the output of the binary adder to generate the desired parity check bits and then combining these check bits with the appropriate ones of the resultant data bit groups. This, however, introduces a significant time delay into the movement of the data through the arithmetic unit. The arithmetic unit must sit and wait for the parity generator to generate the check bits.
It has been heretofore proposed to eliminate or substantially reduce this undesired time delay by using various so-called "parity prediction" techniques. One such proposal suggests the use of parity predictor circuitry which looks at the data bits in the two numbers or operands supplied to the adder and calculates the appropriate parity check bit or bits that will be needed for the result data bits which will appear at the output of the adder. This parity calculation is performed in parallel with and at the same time as the arithmetic operation in the adder. Thus, the appropriate check bits become available at the same time that the result data bits become available. Thus, no time is lost waiting for the parity bits to be generated.
Such previous parity prediction proposals are, unfortunately, not entirely suitable for use in the case of an arithmetic unit which is constructed so as to be able to process binary coded decimal data in zoned or packed format. In the case of zoned decimal data, for example, the data includes more than just numerical digit data. The operands supplied to the arithmetic unit include zone fields as well as digit fields. Also, both zoned decimal and packed decimal operands include a 4 bit sign field which is coded to indicate the polarity or sign of the numerical value represented by the digit fields in the operand. Both of these factors, namely, the presence of zone fields and sign fields, complicate the processing of the decimal data. It requires that the data be given special preconditioning treatment as it enters the arithmetic unit and special postconditioning treatment as it leaves the arithmetic unit. Also, decimal data is processed in binary coded decimal form. Thus, the data being processed is in a base 10 number system, while the binary circuits which handle the binary coded data operate in accordance with the hexadecimal or base 16 number system. This further complicates the processing of the data and requires further special treatment of the data as it enters and leaves the arithmetic unit.
The previously proposed parity prediction techniques of which applicants are presently aware, do not appear to cover these added complications for decimal type data. They appear to relate to the handling of purely binary numbers. They do not appear to be readily applicable to the problems encountered in an arithmetic unit which handles binary coded decimal numbers in zoned or packed format. The present invention, on the other hand, provides a solution to this parity generation problem for the case of such binary coded decimal data. Thus, the present invention fills an important gap that does not appear to be covered by previous proposals.
For a better understanding of the present invention, together with other and further advantages and features thereof, reference is made to the following description taken in connection with the accompanying drawings, the scope of the invention being pointed out in the appended claims.